The present invention relates to computer systems and particularly to the utilization of DDR-II memory with memory interface ASICS for memory subsystem calibration control.
IBM(copyright) is a registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies. JEDEC is the leading developer of standards for the solid-state industry. JEDEC is part of the Electronic Industries Alliance (EIA), that represents manufacturers in all areas of the electronics industry. JEDEC members create standards working together in many committees. Representatives of member-companies, actively participate on these Committees, developing standards to meet the needs of every segment of the industry and their customers. All JEDEC standards are available online at www.jedec.org. While IBM is an active participant in JEDEC committees, the embodiments of the invention described herein makes use of products manufactured according to JEDEC standards but the embodiments of the invention are not known to be or considered to be relevant to the work on any formulating committee.
Data Eye: A graph that plots voltage transitions versus time at a receiver, or multiple receivers. The eye diagram is used to determine the amount of margin a signal or bus has at the receiver. As a signal swings from low to high to low, and high to low to high a characteristic eye is formed at the receiver. The valid data eye is the time that it is valid to sample data at the receiver. Jitter, noise, skew across data bits, etc. will cause the eye to shrink in size.
DIA: A driver impedance adjustment state machine implementing our driver impedance adjustment.
DDR-I: Stands for Double Data Rate DRAM (DDR SDRAM) and is often referenced as DDR and is the subject of a JEDEC standard. This device transmits and receives data at the DRAM on both rising and falling edges of the clock. The clocking mechanism is a separate data strobe signal that is used to sample the data at the DRAM, and it is driven when the DRAM is sending data out to a system.
DDR-II: This is the next generation DRAM (DDR-II SDRAM) after DDR-I and DDR-II is also the subject of a JEDEC standard. DDR-II supports the double data rate features of DDR-I while adding new features. The additional features are the Posted CAS function, off chip driver (OCD) calibration, and on die termination (ODT). These extra parameters improve signal integrity and command bus utilization.
MID: As used here the Acronym refers to a memory interface device. This is a generic DRAM controller that is used to send commands to the DRAM, and it will drive and receive data from the DRAM. DRAM controllers for such purposes have been manufactured before by other companies, such as Intel Corporation for connecting a specific processor. The Intel(copyright) 82845 Memory Controller Hub (MCH) is designed for use with the Intel(copyright) Pentium(copyright) 4 processor in the 478-pin package. The Intel(copyright) 845 chipset contains two main components: the Intel 82845 Memory Controller Hub (MCH) for the host bridge and the Intel 82801BA I/O Controller Hub (ICH2) for the I/O subsystem. The MCH provides the processor interface, system memory interface, AGP interface, and hub interface in an 845 chipset desktop platform. The MCH memory interface can be for use with DDR memory.
OCD: refers to the off chip driver of our preferred embodiment.
Optimal Impedance Setting: The optimal DC setting for the driver impedance of the DRAM is determined to be the settings for which the signal swing of the DRAM driver is minimal, and yet still goes beyond the switching threshold of the MID receiver.
Rank: A term used to refer to the set of DRAM devices that is accessed during a single memory transfer. The number of devices accessed is equal to the size of the data bus divided by the device width of the DRAM. A single chip select line is common for all the devices in a single rank.
Valid Impedance Setting: A valid setting for the driver impedance of the DRAM is any setting that the MID is able to detect all zeros during a pull-down test, and all ones during a pull-up test at the receiver. Upon exit of the algorithm, the state machine will converge on to one of three different options, and set the exit status. Refer to Table 1.
Voh: Driver voltage output high
Vol: Driver voltage output low
Vih: Receiver voltage input high
Vil: Receiver voltage input low
VREF: Voltage reference on a differential receiver. As the input voltage rises above VREF, the output switches from a xe2x80x980xe2x80x99 to a xe2x80x981xe2x80x99. As the input voltage falls below VREF, the output switches from a xe2x80x981xe2x80x99 to a xe2x80x980xe2x80x99. VREF is usually set to half the DRAM driver voltage.
VREF+: Voltage Reference that is higher than VREF. In this application, VREF+ should be set to the voltage level equal to the preferred voltage output high (Voh) of the DRAM driver. Shown in FIG. 3.
VREFxe2x88x92: Voltage Reference that is lower than VREF. In this application, VREFxe2x88x92 should be set to the voltage level equal to the preferred voltage output low (Vol) of the DRAM driver. Shown in FIG. 3.
The new DDR-II DRAM devices now manufactured by JEDEC member companies according to the JEDEC DDR-II standard have been designed such that the output driver impedance of the data bits and data strobes are adjustable for both the pull-up resistance to VDD and pull-down resistance to ground. The JEDEC standards describe how the DRAM must work. However, we are unaware of any JEDEC committee that is defining how the interface ASIC must be designed in order to perform the adjustment for off chip driver OCD calibration. It would be desirable to create a memory interface that would be suitable for use as a generic memory interface device or memory interface ASIC for use with the JEDEC DDR-II standard DRAM as represented, particularly one such as a Samsung(copyright) DDR-II DRAM memory module DIMM, for example, which could be used with a variety of processors. The introduction of the DDR-II DRAM introduced new problems for which there has been no solution. For instance, there were no chip testers which worked with the new DRAM and any memory interface useful for a variety of processors that performed adequate tests. Indeed how was a memory interface with a DDR-II DRAM to be tested? We found that DC testing didn""t account for noise in AC. The data strobe receiver circuit of the DDR-I memory previously was only required to function as a clock output or input and the data strobe for DDR-II does not perform its traditional function. There are two new problems have been introduced: the data strobes must be latched as data, and the data that used to be clocked by these strobes cannot not be so clocked we found. The development of a memory interface ASIC led to many improvements which are detailed herein.
We have provided a memory interface ASIC, and in accordance with the preferred embodiment our off chip driver (OCD) calibration is used by our generic memory interface device to set the driver impedance levels of the DRAM of the JEDEC DDR-II standard type. By adjusting the pull-up drive strength and pull-down drive strength, the output voltage levels and the rise times can be optimized to find the minimal signal swing that is still immune to noise, while not degrading the data eye too severely. We have designed a state machine for the DDR-II off chip driver (OCD) controls that finds the optimal setting for the DRAM Driver Impedance, using both DC and AC methods. The state machine which we developed in accordance with our invention uses an algorithm setting up a procedure for execution with said state machine which selects the optimal impedance settings for the pull-up and pull-down impedance in the DRAM device when it is connected to a memory interface device (MID). Our driver impedance adjustment (DIA) algorithm solves the problem of finding the optimal driver impedance setting by adjusting the value of the driver impedance through a master ASIC, and then sampling the known value sent back from the DRAM. The state machine will stop when the optimal value of the driver impedance is found. The process of the procedure or algorithm has been implemented in the finite state machine we developed and used to automate the process of detecting the optimal driver impedance, and configuring the DRAM module accordingly.
In accordance with the preferred embodiment of our invention we have provided a process implementing a procedure or algorithm in a driver impedance adjustment state machine for both DC and AC modes of operation, and data receiver circuitry used for testing the functionality of DDR-II DRAM off chip driver (OCD) controls.
In DC mode, the driver impedance adjustment (DIA) algorithm solves the problem of finding the optimal driver impedance setting by adjusting the value of the driver impedance through a MID, and then sampling the known value sent back from the DRAM. The state machine will stop when the optimal value of the driver impedance is found. The state machine is used to automate the process of setting the optimal driver impedance in the DRAM module. In accordance with the preferred embodiment of the invention, the optimal driver impedance setting takes into account AC characteristics of the DRAM, therefore ensuring the setting of the driver impedance will work during normal AC operation.
In AC mode, the driver impedance is adjusted to select the optimal setting for the smallest signal swing that still yields a valid data eye. After DC calibration, the output levels of the DRAM driver are set to the lowest pull-up setting that passes, and the highest pull-down setting that passes. This effectively minimizes the switching voltage for the DRAM driver. The AC calibration will check at this setting if the DRAM driver levels are sufficient to support switching reflections and noise that is introduced during real-time operation. This test is done using a combination of the driver impedance adjustments, and running the memory card built in self test (ACBIST).
Prior to DDR-II, the data strobe receiver circuit was only required to function as a clock input. To support the DIA algorithm and OCD DRAM capability of the DDR-II module, the data strobe circuitry was modified to also behave in a mode where it was a data receiver input, therefore requiring the extra circuits to add this special feature to the data strobe circuitry. We added an extra sampling L1/L2 latch at the output of the IO circuit for use with data/data strobe sampling. The problem introduced by the DDR-II product is that during DIA, the data strobe does not perform its traditional function. There are two new problems introduced: the data strobes must be latched as data, and the data that used to be clocked by these strobes must now be clocked in a different manner. We provided a detection circuit to determine if the driver impedance setting is valid. If the setting for the driver impedance is not correct, data will not be transmitted properly between the DDR-II DRAM module and the MID. For testability we have added boundary scan test circuitry at the IO""s. In this implementation of a preferred embodiment a boundary scan receiver latch is used to sample the logic value detected at the IO. This implementation will work for both the data and data strobe pins because each IO has a boundary scan structure required for testability. The boundary scan receiver latch uses a muxed internal core clock to sample the data, rather than its standard test clock. If the setting for the driver impedance is not correct, data will not be transmitted properly between the DDR-II DRAM module and the ASIC that interfaces to it. The detection circuit will identify the validity of a driver impedance adjustment (DIA) setting. If the DRAM is in pull-up mode, then the DRAM module will drive back all xe2x80x981xe2x80x99s when queried. If the ASIC receiver does not detect all xe2x80x981xe2x80x99s at the IO device, the detection circuit will register a fail. The pull-down case is the same as the pull-up, except that the DRAM will drive back all xe2x80x980xe2x80x99s when queried and the detection circuit will register a fail if there is not all logic xe2x80x980xe2x80x99s at the IO circuits. The detection circuit solves the problem of knowing whether or not a valid setting is being used.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.